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Patent # Description
US-4,332,026 Multiple data rate digital switch for a TDMA communications controller
A multiple data rate digital switch for a TDMA communications controller is disclosed which can service a plurality of input/output ports having many different...
US-4,330,857 Dynamically variable priority, variable position channels in a TDMA burst
The position of a channel of information transmitted from a particular port is varied in response to the changing priority of that port's messages as time...
US-4,329,186 Simultaneously forming fully implanted DMOS together with enhancement and depletion mode MOSFET devices
A semiconductor fabrication process and the resulting structure is disclosed for an FET device with a precisely defined channel length. Two process embodiments...
US-4,328,543 Control architecture for a communications controller
A control architecture is disclosed for a communications controller, for connecting a control processor in the communications controller to a plurality of...
US-4,326,212 Structure and process for optimizing the characteristics of I.sup.2 L devices
An improved I.sup.2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and...
US-4,322,845 Demand assignment technique for TDMA satellite communication network
In a time division multiple access satellite communication system, a reference station which allocates channel capacity also regulates demand by the ground...
US-4,320,504 Mechanism for synchronization of data ports in TDMA communication
The transmission and reception pattern generators are synchronized for all data ports operating at the same data rate throughout an entire TDMA system. This...
US-4,319,353 Priority threaded message burst mechanism for TDMA communication
To make the most efficient use of the TDMA frame for a satellite communications network, the assignment of each local station's TDMA burst duration is based on a...
US-4,315,330 Multiple data rate testing of communication equipment
The invention finds application in a TDMA communications controller having a plurality of i input/output ports. The input/output ports transfer data from...
US-4,314,267 Dense high performance JFET compatible with NPN transistor formation and merged BIFET
A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a...
US-4,307,461 Call processor for a satellite communications controller
A call processor is disclosed for a satellite communications controller, having a plurality of M voice ports, with an E lead input and an M lead output connected...
US-4,299,888 Method for forming in situ magnetic media in the form of discrete particles and article
A method of forming discrete magnetic particles in situ by dispersing a nickel hypophosphite solution in a binder and binder solvent, such as polyvinyl alcohol...
US-4,295,217 Apparatus to reduce the effect of a mid-talkspurt freeze-out
In reconstructing the analog waveform from a syllabically companded delta modulated digital signal transmitted over a TDMA communication channel operating at...
US-4,289,834 Dense dry etched multi-level metallurgy with non-overlapped vias
A double level metal interconnection structure and process for making same are disclosed, wherein an etch-stop layer is formed on the first metal layer to...
US-4,285,064 TDMA Satellite communication system
A time division multiple access satellite communication architecture is disclosed to achieve a relatively simple control procedure for permitting multiple...
US-4,280,855 Method of making a dual DMOS device by ion implantation and diffusion
A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L.sub.D...
US-4,280,197 Multiple access store
A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single...
US-4,275,968 System for controlling and sequencing a printer
Printer having a sheet feed and drum transport assembly and an array transport assembly, these assemblies having critical operating parameters whose profile is...
US-4,267,465 Circuit for recharging the output nodes of field effect transistor circuits
A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit...
US-4,267,407 Method and apparatus for the transmission of speech signals
For the multiplex transmission of coded speech signals in periodic frames, single segments (blocks of coded samples) are selectively suppressed for redundancy...
US-4,264,832 Feedback amplifier
This is a feedback amplifier incorporating shunt feedback pairs which are emitter coupled for differential input transimpedance configuration whose ...
US-4,262,356 Method and system for synchronizing a TDMA communication network comprising a satellite equipped with several...
A method and a system are disclosed for synchronizing within a recurrent time frame the starting points of the transmissions from the various stations in a TDMA...
US-4,262,331 Self-adaptive computer load control
A self-adaptive computer load control apparatus and method are disclosed for allocating servicing time by a Central Processing Unit (CPU) to several Peripheral...
US-4,262,316 Record storage apparatus
For producing a transducer access opening in a stack of rotating flexible magnetic record disks, a co-rotating part axially deflects the peripheral edges of...
US-4,259,366 Fabrication method for forming FET gate electrode
A merged AND/OR array PLA is disclosed wherein the merger is accomplished by forming the gates of the FET devices in the AND array by means of an upper conductor...
US-4,253,775 Apparatus for re-inking a ribbon in a thermal transfer printing system
A doctor blade is used to apply a powdered toner to the depleted regions of a resistive thermal transfer ribbon. The ribbon is then moved adjacent a heating...
US-4,238,842 LARAM Memory with reordered selection sequence for refresh
A computer paging store memory utilizing line addressable random access memories (LARAM) including charge coupled device (CCD) shift registers in which data is...
US-4,188,649 Magnetic head having a jagged-edged gap, and method for producing such head
An AC magnetic erase head having improved AC erase characteristics, the magnetic head being formed of two half core elements of a magnetic material, preferably...
US-4,070,501 Forming self-aligned via holes in thin film interconnection systems
A method for forming self-aligned via holes which are used to interconnect levels of thin films atop substrates. A first level thin film pattern, typically...
US-4,069,488 Computer controlled distribution apparatus for distributing transactions to and from controlled machines tools
A system for controlling a plurality of machine tools in which the central processor communicates data transactions to and from a plurality of tool controllers,...
US-4,062,040 Field effect transistor structure and method for making same
An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a...
US-4,060,427 Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor...
US-4,058,887 Method for forming a transistor comprising layers of silicon dioxide and silicon nitride
A method of manufacturing an insulated gate field effect transistor comprising providing a semiconductor body portion of one type conductivity, providing on a...
US-4,056,846 Data processing system with apparatus for sharing channel background processing
In a data processing system having a plurality of channels that are organized for separately processing the operations of specific I/O devices and the operations...
US-4,055,219 Electric tip-off heat sink
During the construction of display gas panels front and back panels are connected together by means of a seal which forms a chamber for receiving a display gas....
US-4,053,948 Look aside array invalidation mechanism
A virtual memory system is described in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual...
US-4,053,942 Device for removing low level contaminants from a liquid
A device for removing contaminant impurities, particularly contaminants existing at very low levels, from a liquid, including a heating element at least...
US-4,053,925 Method and structure for controllng carrier lifetime in semiconductor devices
The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment...
US-4,051,273 Field effect transistor structure and method of making same
An improved field effect transistor structure which reduces a leakage phenomenon, termed the "sidewalk" effect, between the semiconductor substrate and a...
US-4,049,478 Utilization of an arsenic diffused emitter in the fabrication of a high performance semiconductor device
A substantially square N-type impurity distribution profile in a silicon substrate produces much superior dc and ac characteristics in PN junction devices than...
US-4,048,671 Address match for data processing system with virtual addressing
Apparatus for signalling the occurrence of a match between an address that is supplied to a control store and an address that is to be watched for in a data...
US-4,045,736 Method for composing electrical test patterns for testing AC parameters in integrated circuits
A method is provided for generating electrical test patterns for testing functional AC parameters of integrated semiconductor circuits from the test patterns...
US-4,045,594 Planar insulation of conductive patterns by chemical vapor deposition and sputtering
A method using a chemically vapor deposited (CVD) insulator to form a substantially planar layer of insulative material atop a conductive pattern on the surface...
US-4,044,454 Method for forming integrated circuit regions defined by recessed dielectric isolation
In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially...
US-4,040,891 Etching process utilizing the same positive photoresist layer for two etching steps
In integrated circuit fabrication a method is provided involving the utilization of the same positive photoresist layer to form two different masks used in two...
US-4,039,867 Current switch circuit having an active load
An improved current switch circuit having an active load. The active load comprises a current source at the collectors of the switch transistors which generates...
US-4,038,110 Planarization of integrated circuit surfaces through selective photoresist masking
An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary...
US-4,035,767 Error correction code and apparatus for the correction of differentially encoded quadrature phase shift keyed...
This specification describes a convolutional code and apparatus for the correction of errors in differentially encoded quadrature phase shift keyed data (DQPSK)....
US-4,035,607 Integrated heater element array
A thermal display comprising an array of semiconductor heater mesas having a larger cross-sectional area at the display surface than at the support surface. The...
US-4,035,276 Making coplanar layers of thin films
A method for forming coplanar thin films, particularly conductor-insulator patterns, on a substrate. A pattern which includes a first thin film and an expendable...
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