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Patent # Description
US-4,034,469 Method of making conduction-cooled circuit package
A circuit package exhibiting an excellent heat transfer path from a semiconductor chip or other heat-generating device to the heat-sink can or cover of the...
US-4,034,468 Method for making conduction-cooled circuit package
A method for making a circuit package which exhibits an excellent heat transfer path from a semiconductor chip or other heat generating device to the heat sink...
US-4,034,356 Reconfigurable logic array
This specification describes a set of arrays for performing logic function in various subsets of the original set. The array structure is characterized by a...
US-4,032,962 High density semiconductor integrated circuit layout
An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less...
US-4,032,058 Beam-lead integrated circuit structure and method for making the same including automatic registration of...
A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive...
US-4,031,519 Printer
A printer responds to channel commands including coded data received over a channel from a data processing unit by printing characters represented by the coded...
US-4,029,999 Thermally conducting elastomeric device
A thermally conducting cushion-like elastomeric pad of RTV (Room Temperature Vulcanized) silicone rubber moled with indentations in one surface to fit in...
US-4,029,970 Changeable decoder structure for a folded logic array
This specification describes a decoder for a programmable logic array (PLA) having opposite ends of input lines of the array connected to outputs of different...
US-4,029,562 Forming feedthrough connections for multi-level interconnections metallurgy systems
A method for forming feedthrough connections, or via studs, between levels of metallization atop semiconductor substrates. A first level conductive pattern is...
US-4,028,717 Field effect transistor having improved threshold stability
An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the...
US-4,028,150 Method for making reliable MOSFET device
A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by...
US-4,028,149 Process for forming monocrystalline silicon carbide on silicon substrates
A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous...
US-4,027,321 Reliable MOSFET device and method for making same
A substantial increase in the reliability of metal-oxide-semiconductor field effect transistor (MOSFET) devices having a thin gate dielectric is achieved by...
US-4,025,909 Simplified dynamic associative cell
This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected...
US-4,025,799 Decoder structure for a folded logic array
This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to...
US-4,023,197 Integrated circuit chip carrier and method for forming the same
An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularities at the various levels...
US-4,020,470 Simultaneous addressing of different locations in a storage unit
Two separate address lines are provided for each storage line of local storage. One address line is connected to a first group of bytes and the second address...
US-4,020,466 Memory hierarchy system with journaling and copy back
This hierarchical memory system has two memory units on each level. One of the units called the data store contains all the data at that level of the memory. The...
US-4,020,460 Method and apparatus of checking to determine if a signal is present on more than one of n lines
This specification describes an apparatus for determining if more than one of n lines are up at a given time. The apparatus includes means for encoding the n...
US-4,018,496 Interconnection for conductor assemblies having closely spaced conductive lines
A set of closely spaced, parallel conductive lines on an insulating support are located in face to face electrical contact with a corresponding set of conductive...
US-4,017,883 Single-electrode charge-coupled random access memory cell with impurity implanted gate region
A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused...
US-4,017,762 Voltage controlled sustain frequency in a gas display panel
A circuit for supplying sustain voltage pulses to the orthogonal conductors of a gas display panel including voltage sensors to sense any change in sustain...
US-4,016,396 Precision tool and workpiece positioning apparatus
Apparatus for positioning a workpiece and tool in a precise location relative to each other by positioning in a predetermined site the workpiece, and then...
US-4,014,036 Single-electrode charge-coupled random access memory cell
A charge-coupled random access memory cell is formed in a semiconductor body divided into three adjacent regions. The first region has an impurity diffused...
US-4,013,891 Method for varying the diameter of a beam of charged particles
In the bombardment of targets with beams of charged particles, a method for varying and controlling the diameter of such beams by passing the beam through an...
US-4,011,449 Apparatus for measuring the beam current of charged particle beam
In an ion implantation apparatus, a structure for measuring the beam current at the target wherein a Faraday Cage is formed by walls adjacent to and electrically...
US-4,009,472 Dynamic associative cell
This specification describes an associative memory cell capable of performing logic functions. The cell comprises two transistors with their collectors connected...
US-4,009,469 Loop communications system with method and apparatus for switch to secondary loop
This invention relates to a system for communicating between a central station, such as a host processor, and one or more remote stations, such as terminal...
US-4,009,338 Tablet with improved pen height compensation
An improved operation is provided for a graphic tablet of the type in which a pen is capacitively coupled to sets of X dimension wires and Y dimension wires that...
US-4,007,103 Planarizing insulative layers by resputtering
A method of planarizing an electrically insulative layer formed over a non-planar integrated circuit substrate having raised portions. After the electrically...
US-4,002,511 Method for forming masks comprising silicon nitride and novel mask structures produced thereby
In the fabrication of integrated circuits, a method is provided for forming masking structures comprising silicon nitride which avoids the stresses and...
US-3,999,214 Wireable planar integrated circuit chip structure
A planar semiconductor integrated circuit chip structure comprising a surface from which a plurality of regions of different conductivity types extend into the...
US-3,999,012 Graphic entry tablet with improved addressing
An improved tablet system is disclosed of the type having an array of X dimension wires and Y dimension wires that are capacitively coupled to a pen that a user...
US-3,997,963 Novel beam-lead integrated circuit structure and method for making the same including automatic registration of...
A beam-lead integrated circuit chip structure which comprises a semiconductor chip substrate having a passivated planar surface from which active and passive...
US-3,995,301 Novel integratable Schottky Barrier structure and a method for the fabrication thereof
A novel Schottky Barrier structure which is integratable with standard integrated circuits comprising a metal layer of Al.sub.2 Pt in contact with a high...
US-3,993,934 Integrated circuit structure having a plurality of separable circuits
A method for determining whether an integrated circuit chip containing a plurality of separable circuits is operable when one or more of the separable circuits...
US-3,993,919 Programmable latch and other circuits for logic arrays
This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch...
US-3,992,712 Method and apparatus for recording information on a recording surface
A plurality of magnetic liquid streams is simultaneously excited to produce a plurality of streams of magnetic droplets of substantially uniform spacing and...
US-3,992,637 Unclocked sense ampllifier
This specification describes a differential sense amplifier serving balanced sense lines. An imbalance in bias potential on the sense lines holds the sense...
US-3,992,579 Tablet system with digital activation
An improved tablet system is disclosed of the type having an array of X and Y dimension wires that are capacitively coupled to a pen that a user holds to the...
US-3,984,582 Method for preparing positive resist image
A positive resist image is produced by exposing, to radiation in a predetermined pattern, a polymeric material containing polymerized alkyl methacrylate units...
US-3,983,547 Three-dimensional bubble device
A three-dimensional magnetic bubble device formed by depositing, on a flexible substrate, a plurality of pseudo-chips of amorphous metallic film capable of...
US-3,983,419 Analog waveform transducing circuit
An analog waveform transducing circuit is disclosed which includes a pair of superconductive circuits connected in parallel between a pair of terminals. One of...
US-3,983,023 Integrated semiconductor circuit master-slice structure in which the insulation layer beneath unused contact...
A planar integrated semiconductor circuit master-slice structure in which the insulation layer over the planar surface remains intact and free of undesirable...
US-3,982,967 Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths
In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation...
US-3,982,943 Lift-off method of fabricating thin films and a structure utilizable as a lift-off mask
A method for use in forming thin film patterns in the fabrication of integrated circuits. The method involves depositing a bottom layer of positive photoresist...
US-3,982,316 Multilayer insulation integrated circuit structure
A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of...
US-3,982,251 Method and apparatus for recording information on a recording medium
Streams of ink droplets are formed of a material which changes from transparent or colorless to a color when subjected to a selected energy source. A print...
US-3,981,844 Stable emulsion and method for preparation thereof
An emulsion of water; a water immiscible liquid including a solution of a liquid nonpolar hydrocarbon and a liquid halogenated aliphatic hydrocarbon; and a...
US-3,976,992 Gas display panel with light pen
An improved light pen is provided for a gas display panel of the type in which an alternating polarity sustain voltage produces a succession of brief light...
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